DDR noise measurements require creating effective noise patterns. Simple random patterns might not show significant crosstalk or simultaneous noise. For power integrity measurements, one should excite the DQ bus with resonance frequency measured on the pad of the bypass capacitors. Both Tektronix and Agilent provides DDR probing solutions using interposer which sits between the PCB and the DDR package.
The accuracy of the waveform is difficult to verify in some cases. Moreover, the access to the probing locations can be difficult without flexible probe holder.
DDR System Probing Tips
- High speed signaling creates many reflections on the interconnect. The probing point should be set close to the receiver pin. For example, probe the DDR via for the memory write operation, and probe ASIC pin for memory read mode.
- Probe the worst case signals can be achieved by selecting the signals with the worst SI environment. A worst pin out of 64 data bus can be identified by simulation software (e.g. Mentor Graphics) or by engineering judgment.
- To measure setup/hold time violations, the first burst usually has the worst timing.
- The bus turn-around between write and read operation can create the worst power noise.
- It is essential to remember that DDR has large setup/hold requirements. A large eye opening may still fail to meet the timing specifications.
DDR Probing Demonstrations
DDR probing with high-speed oscilloscope
Probing DDR in a vertical chassis